Low Power & Area Multiplier for Deep Learning Applications
نویسندگان
چکیده
منابع مشابه
Design and Implementation of Compact Booth Multiplier for Low power, Low Area & High Speed Applications
Presently, the design of a compact multiplier is playing a vital role in the stream of VLSI signal processing, DSP, Modern wireless communication etc. The main goal of this proposal is to design a compact booth multiplier by using modified radix4 recoding and an efficient finite state machine (FSM) to achieve small chip size and low delay utilization. In the existing technique, compression base...
متن کاملLow Truncation Error and Area Efficient Multiplier for Cryptographic Applications
Multipliers play a vital role in many cryptographic applications like elliptic curve cryptography, RSA and other algorithms. The direct truncation of least significant part of the product leads to large error in the resultant product when fixed width output is the requirement. This paper proposes a truncation error minimizing logic which greatly reduces truncation error. Truncation error minimi...
متن کاملImproved Mitchell-Based Logarithmic Multiplier for Low-power DSP Applications
This paper presents a method to improve the accuracy of a logarithmic multiplier, based on Mitchell’s algorithms for calculating logarithms and antilogarithms. The method developed offers an area saving of approximately 50% and a power saving of 71% for larger input widths. A filter based on the multiplier is also presented. Introduction Multiplication in hardware has always been a cumbersome p...
متن کاملArea Efficient Low Power Vedic Multiplier Design Using GDI Technique
Multipliers consume maximum amount of power during the partial product addition. For higher order multiplication, a huge number of adders are used to perform the partial product addition. Using compressor adders, that can add four, five , six or seven bits at a time, the number of full adders and half adders can be reduced and thus area and power consumed also gets reduced. These compressor add...
متن کاملCompressor Based Area-Efficient Low-Power 8x8 Vedic Multiplier
Multipliers are the integral components in the design of many high performance FIR filters, image and digital signal processors. Multipliers being the most area and power consuming elements of a design, area-efficient low-power multiplier architectures are in demand. In this paper, multiplier based on ancient Vedic mathematics technique has been proposed which employs 4:3, 5:3, 6:3 and 7:3 comp...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Bioscience Biotechnology Research Communications
سال: 2020
ISSN: 0974-6455,2321-4007
DOI: 10.21786/bbrc/13.14/101